(1) Field of the Invention
The present invention generally relates to broadband integrated services digital networks and, more particularly, to a broadband integrated services digital network using an HIPPI (High-Performance Parallel Interface).
(2) Description of the Prior Art
Recently, a high-bit-rate data transfer interface called HIPPI has been proposed. The HIPPI is capable of transferring 800 Mbps of data, and is proposed for use, for example, as a high-speed transfer path of a super computer. A data transfer system is now planned in which computers and terminals in conformity with the HIPPI are coupled to each other via a high-speed network called a BISDN (Broadband Integrated Services Digital Network). Such a BISDN can be established by using, for example, an ATM (Asynchronous Transfer Mode) network.
FIG. 1 is a block diagram of a proposed HIPPI (see "HIGHPERFORMANCE PARALLEL INTERFACE" X3T9/88-127 X3T9.3/88-023 REV 7.0, Dec. 11, 1989, the disclosure of which is hereby incorporated by reference). An HIPPI terminal 10 and an HIPPI terminal adapter (TA) 12 are connected to each other via a group of interface lines 11. The interface lines 11 include a data line, a request line, a connect line, two interconnect lines, a ready line, a burst line, and a packet line. 32-bit parallel data is transferred via the data line. A request to transfer data to the terminal adapter 12 from the terminal 10 is transferred via the request line. The connect line turns ON (switches to a high level) when the terminal adapter 12 switches to a state in which it can accept data. The interconnect line extending from the terminal adapter 12 informs the HIPPI terminal 10 that power supply to the terminal adapter 12 has been turned ON. The interconnect line extending from the HIPPI terminal 10 informs the terminal adapter 12 that power supply to the HIPPI terminal 10 has been turned ON. The terminal adapter 12 informs, via the ready line, the HIPPI terminal 10 that the terminal adapter 12 is ready to receive data. The burst line is ON (maintained at a high level) while the HIPPI terminal 10 is transmitting burst data to the terminal adapter 12. The packet line is ON (maintained at a high level) while the HIPPI terminal 10 is transmitting a packet to the terminal adapter 12.
FIG. 2 shows a frame hierarchy of data which is transferred via the above-mentioned interface. The frame hierarchy has a layer called "connection". Each connection comprises a plurality of packets. Each packet comprises a plurality of bursts, each containing about 1K bytes of data.
During data transfer, the request line and the interconnect lines are ON. After than, a ready pulse is generated so that the terminal adapter 12 turns ON the ready line and then turns OFF the ready line. Then, the HIPPI terminal 10 can transmit burst data to the terminal adapter 12 via the data line. The terminal adapter 12 can send, before receiving burst data, to the HIPPI terminal 10 ready pulses equal in number to the number of bursts which the terminal adapter 12 can receive. As has been described previously, the bit rate of data transferred between the HIPPI terminal 10 and the terminal adapter 12 is 800 Mbps.
An ATM network is suitable for use as a network which transfers data at a high bit rate, such as 800 Mbps. FIG. 3 is a block diagram of a BISDN which utilizes an ATM network. The above-mentioned HIPPI terminal 10 is coupled to an ATM network 14 via the terminal adapter 12. Similarly, an HIPPI terminal 18 is coupled to the ATM network 14 via an HIPPI terminal adapter 16. Data is transferred via the ATM network 14 in cell units. Each cell is, for example, 53-byte data which is composed of, for example, a header consisting of 5 bytes, and information of 48 bytes.
FIG. 4 is a diagram showing a data transfer sequence in which the HIPPI terminal 10 functions as a transmitter terminal and the HIPPI terminal 18 functions as a receiver terminal. The receiver terminal 18 sends the ready pulse to the terminal adapter 16, which sends to the terminal adapter 11, via the ATM network 14, a message which shows that the receiver terminal 18 has generated the ready pulse. In response to the message, the terminal adapter 11 sends a ready pulse to the transmitter terminal 10.
The transmitter terminal 10 transmits the first burst data #1 to the terminal adapter 11, which disassembles the first burst data #1 into a plurality of cells and sends these cells to the terminal adapter 16 via the ATM network 14. The terminal adapter 16 assembles the cells into burst data, which is output to the receiver terminal 18. In the sequence shown in FIG. 4, two ready pulses are successively sent to the transmitter terminal 10. Each time one ready pulse is received, the transmitter terminal 10 sends one burst to the receiver terminal 18. The receiver terminal 18 generates a further ready pulse, after receiving the two burst data #1 and #2. In this manner, burst data is transferred from the transmitter terminal 10 to the receiver terminal 18.
As described above, the transmitter terminal 10 does not send burst data to the receiver terminal 18 until the transmitter terminal 10 receives the ready pulse from the receiver terminal 18 which is in the burst receivable state. It should be noted that there is a delay in the receipt by terminal adapter 11 and terminal 10 of the ready pulse generated by the receiver terminal 18. In other words, the ATM network 14 introduces a delay in the transfer of data. Hence, the transmitter terminal 10 does not efficiently send burst data to the receiver terminal 18. Further, if the ready pulse is discarded due to a congestion in the ATM network 14 or a failure in the communication system, the number of bursts recognized by the transmitter terminal 10 as being transmittable by the transmitter terminal 10 will be different from the number of bursts which is recognized to be receivable by the receiver terminal 18. In this case, the receiver terminal 18 sends the ready pulse to the transmitter terminal 10 and waits for burst data, even though the transmitter terminal 10 cannot send burst data to the receiver terminal 18 since the transmitter terminal 10 has not received the necessary ready pulse. In this case, the communication system reaches a deadlocked state.